• Contenu
• Ouessant HowTos: Quickstart
  • First simulation
    • Requirements
    • Getting started: setting up Ouessant environment
  • Going further
    • Going further: modifying the project
    • Getting started: run Ouessant on a FPGA

Ouessant HowTos: Quickstart¶

This page is still a Work in Progress. Feel free to signal any mistake/lack in the description.

First simulation¶

Here are the required steps to set a Ouessant based system up. For now, only Leon based platforms are possible

Requirements¶

In order to use Ouessant, a few tools are needed.

The Ouessant code base and build architecture relies on GNU/Linux common building tools. We do not support Windows as a development platform. On a Debian/Ubuntu GNU/Linux distribution, you can get the required tools with the following command:

sudo apt-get install build-essential gcc make git bison flex 

Ouessant is a hardware design, thus CAD tools are needed according to your needs:

• if you want to work in simulation, ModelSim is required.
• if you want to work with Xilinx FPGA, ISE toolsuite with a valid license for the board you are using is required. Please note that for Nexys4 and Atlys board, ISE WebPack is sufficient. You will also need tools to program the board (impact for Xilinx, Adept for Digilent boards).

Furthermore, you will need the tools for the processor you are working with. For LEON based SoC, this means :

• the compiler(s) for the SPARC processor (Linux or/and bare (​http://www.gaisler.com/index.php/downloads/compilers?task=view&id=161) according to your needs)
• the GRMON debugger (​http://www.gaisler.com/index.php/downloads/debug-tools?task=view&id=190)

We assume that all those tools are available, and correctly configured. Please refer to the corresponding manuals if you need more information. Boards specific instruction for supported devices are provided in [OuessantBoards|the Ouessant boards page].

Getting started: setting up Ouessant environment¶

1. Download the project repository:
   

   git clone https://redmine.telecom-bretagne.eu/git/ouessant/ 

1. Go to the project's root (ie. the folder you have just created by cloning the repository). If you put it in your home directory, you can do this by typing :
   

   cd ~/ouessant

2. Set up the Ouessant environment:
   

   make env

   
   This will clone all necessary files from the git.
   Warning : make sure that you have all the required permissions on the ouessant folder.

We provide as much automation as possible to speed up the process of getting a Ouessant processor up and running. You can get all available commands and help by typing make help in the command line.

The code is divided in 5 main directories (other directories will be described later):

• ocp contains the main VHDL code for Ouessant,
• drivers has all the example codes in it, for Linux and baremetal
• socs is the main directory for complete example System on Chips
• scripts contains tools for automation
• tools is created to store tools for Ouessant, mainly the assembler

When you run the make env command, you download all required tools (especially the Leon tools), generate the Ouessant configurations, and compile the tools. You are now ready to compile a complete SoC with associated software, and run your first test.

Simulate a first Leon design
We are now going to simulate a Spiral FFT design using Ouessant. # Go to the leon3-ouessant-mst-minimal folder by typing:

cd socs/leon3-ouessant-mst-minimal/

and compile the project by running

make vsim

By default, this will compile a Leon processor with required peripherals, and a Ouessant with a Spiral DFT (256 points) accelerator. Further information on how to change this design are given in the "Going further" section. # The design is now compiled, we can compile the associated code. This is done by running

 make install 

which will compile the code and create the RAM image for the design. # Finally, type

make vsim-launch

to launch the simulation. This will launch ModelSim with the compiled design.
You can then launch the simulation. We provide a complete wave configuration to show what is going on inside Ouessant. Type

 do wave.do
         run 30 ms
   

to start the simulation. The device starts to do things around 1.6 ms. You should see the first result output around 2 ms, and the first values around 4.7 ms. This takes a few minutes to reach depending on your machine.

Going further¶

Going further: modifying the project¶

Congratulations, you launched your first Ouessant project!

You can now modify it if you want to suit your need.

If you open the leon3mp.vhd file, you will see the top for this design. You can modify the Ouessant instantiation in it (called ouessant0). For example, you can change the orac generic parameter to suit your need.

You can also modify the test source code by editing the systest.c file. For the moment, no Ouessant compiler exists, and the microcode must be written directly in binary.

Getting started: run Ouessant on a FPGA¶

For now, Ouessant is available on Atlys and Nexys4 boards, only with a Leon project.

1. If you want to load your project on FPGA, you first have to connect it to your computer and to turn it on.
2. Go into the SoC design corresponding to your FPGA~/ouessant/design/leon3-ouessant-digilent-atlys/ and make sure there is the right version of leon3mp.vhd and systest.c.
3. Type the following command line "make ise-prog-fpga". This will compile all vhd files for your Digilent Atlys FPGA. Please note that you should have Adept already installed.
4. Type the following command line "sparc-elf-gcc systest.c -o systest". This will cross compile your C file into a binary stream for your FPGA.
5. Connect your FPGA to your computer using its IP address via Network Manager for instance.
6. Type the following command line "grmon -eth XXX.XXX.X.XX" where XXX.XXX.X.XX is your FPGA's IP address. The LED at the right of your FPGA should be on.
7. Open PuTTY by typing "putty" in your terminal. Please note that you should have PuTTY already installed.
8. Fill the Host Name field with "/dev/ttyACM0" and the port name with "38 400".
9. To make sure that you're correctly connected, click on the reset button on your FPGA. A short message should pop on the PuTTY terminal.
10. Now you can load your program by typing the following command line in the GRMON terminal load systest.exe.
11. Finally, you can run your program simply by typing "run" in the GRMON terminal.
12. When you're done, you can exit the GRMON terminal by typing "quit".

Have fun !